Events
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Feb 24 6PM-7:30PM Member/Open Meeting at Santa Clara University - with Pizza: As we progress into 2026, we begin with our SCV/OEB SSIT Chapter and ISTAS25 follow-up on 24 February, 2026, from 6.00 pm to 7.30 pm in an hybrid mode. This is a member/open meeting at Santa Clara University to share information on the SSIT Chapter Officer Election Status and to encourage others to formally join our SSIT Chapter as part of their IEEE Membership. Moreover, it will also function as the ISTAS25 follow-up to explore the possibility of a Special ISTAS25 Issue of Technology & Society periodical/magazine and to plan for future SSIT events. Agenda: AGENDA - Various types of Pizza and drinks will be served - Introductions - SSIT Officer Status - ISTAS25 Conference Follow-up - Chapter Focus Areas Alignment Discussion - for 2026 meeting presentations and involvement - AI Related Topics - ISTAS25 follow-up - your ideas welcome - STEM engagement with YP Involvement - Support of Techs on Decks at the USS Hornet - Sustainability Topics - Wrap-up and Actions Room: 2116, Bldg: Sobrato Campus for Discovery and Innovation (SCDI), Santa Clara University, 500 El Camino Real, Santa Clara, California, United States, 95050, Virtual: https://events.vtools.ieee.org/m/536833 |
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Advances in intelligent computing are redefining how we discover therapeutics and engineer regenerative tissues. This talk presents two complementary, algorithm-driven approaches aimed at transforming treatments for neurological and skeletal disorders. First, we introduce a computational peptidomics pipeline that mines genomic data to identify precursor sequences encoding neuroactive peptides, which are key modulators of signal transmission that bind heptahelical receptors. Traditional peptide discovery is slow and serendipitous; our algorithms predict peptide maturation pathways, including post-translational modifications, and pair these predictions with a high-sensitivity assay capable of detecting receptor-generated second messengers such as InsPs and cAMP. This integrated strategy has yielded promising peptide-based drug candidates for Parkinson’s disease and Osteoporosis, now advancing through animal testing. Parallel to this, we present a bioengineering framework for creating biomimetic, biocompatible bone scaffolds. Using uCT images of osteoporotic bone, we design and 3D-print trabecular structures optimized for both mechanical strength and osteoconductivity, addressing limitations of current synthetic scaffolds. These engineered matrices, enhanced by the osteogenic Calcitonin Receptor Fragment Peptide, support robust osteoblast growth and functional bone formation. Together, these innovations illustrate how algorithmic design and intelligent technologies can accelerate next-generation healing, from molecular therapeutics to regenerative tissues. Co-sponsored by: Vishnu S. Pendyala, SJSU Speaker(s): Dr. Vishnu S. Pendyala, Prof. Srinivas Pentyala Virtual: https://events.vtools.ieee.org/m/538191
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The semiconductor sector continues to expand rapidly, supported by growing needs in AI, automotive electronics, and consumer devices. As the limits of traditional scaling become increasingly evident with both physically and economically, advanced packaging is taking center stage as a critical driver of higher performance, tighter integration, and further miniaturization. In this context, next-generation packaging platforms such as panel-level packaging (PLP) and glass core substrates are emerging as key technologies shaping the industry's future direction. PLP is gaining industry interest for its potential to reduce manufacturing costs and support ultra-large form-factor package. Nevertheless, its adoption introduces several materials and process challenges, including warpage management, thermal robustness, and process compatibility. To overcome the warpage issue, alternative material like glass core substrate is being explored for its exceptional dimensional stability and favourable electrical characteristics. Despite core cores advantages, the use of glass raises practical concerns in handling, via creation, and integration within existing assembly infrastructures. This presentation will delve into these evolving technology pathways, examining market motivations, supply-chain considerations, and the broader ecosystem shifts surrounding them. It will outline both the opportunities these solutions present and the technical barriers that must be overcome as advanced packaging moves into its next phase of development. Co-sponsored by: Benson Chan Speaker(s): YY Tan, Agenda: See LOCATION tab for WebEx info Virtual: https://events.vtools.ieee.org/m/541765
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SCV WIE Feb 2026 ExCom ieeescvwie is inviting you to a scheduled Zoom meeting. Join Zoom Meeting https://us06web.zoom.us/j/87970173125?pwd=jmBrqlVYgnQ5jdmcRcJ1aH7ZQcBRX4.1 Meeting ID: 879 7017 3125 Passcode: 229065 --- One tap mobile +16699006833,,87970173125#,,,,*229065# US (San Jose) +16694449171,,87970173125#,,,,*229065# US Join instructions https://us06web.zoom.us/meetings/87970173125/invitations?signature=8IF6K5pz-R3xdls0sOEWYH9eNDEPHsCtib3HTHLA4KU When Thursday Feb 26, 2026 ⋅ 6pm – 7pm (Pacific Time - Los Angeles) Location https://us06web.zoom.us/j/87970173125?pwd=jmBrqlVYgnQ5jdmcRcJ1aH7ZQcBRX4.1 Agenda: - New member introductions - Past Events - Upcoming Events - Other agenda items Virtual: https://events.vtools.ieee.org/m/540508 |
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As part of the Stanford IEEE continuing Speaker Series throughout the year. Stanford, California, United States, 94305 |
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2nd Lecture of IEEE CS San Diego's 2026 Invited Seminar Series (Virtual) Co-sponsored by: Media Partner: Open Research Institute (ORI) Speaker(s): Dr. Aniket Roy Agenda: - Invited talk from Dr. Aniket Roy, from NEC Labs America - Q/A Session Virtual: https://events.vtools.ieee.org/m/540255 |
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Greetings and welcome to our annual IEEE San Francisco Bay Area Consumer Technology Society (CTSoc) event, bringing a comprehensive summary of latest and most innovative technologies unveiled at the 2026 Consumer Electronics Show (CES) in Las Vegas. CES has long been the world's premier showcase for consumer technology, and its scope continues to expand well beyond traditional consumer electronics across a diverse range of categories—from wearables and smart home ecosystems to autonomous robotics, commercial and recreational drones, cutting-edge medical and healthcare devices, automotive technology, sustainable energy and accessibility innovations, that are reshaping how we live, work, and interact with the world around us. Please join us as our expert speakers distill the most significant trends and breakthrough technologies from the show. Speakers: Tom Coughlin: President, Coughlin Associates 2024 IEEE President & IEEE Fellow, Tom is a world-renowned digital storage expert and industry analyst. Having served as the global leader of IEEE, he brings unparalleled insight into the hardware and infrastructure driving the latest consumer trends. Avery Lu: Partner & Head of Business Development, Aventurine Capital Group 2025-2026 Chair of the IEEE Santa Clara Valley Section, Avery is a seasoned venture capitalist and deep-tech executive. His expertise in semiconductors and AI allows him to identify the startups and technologies with the highest potential for commercial success and market disruption. This will be a hybrid event (in-person and online). Register early, do not miss this event to get a glance into the future of consumer technologies. In-Person joining locations - Plug and Play Tech Center, Sunnyvale, San Francisco Room 440 N. Wolfe Road, Suite 71, Sunnyvale, California, United States 94085 Online Webex joining links - https://ieeemeetings.webex.com/ieeemeetings/j.php?MTID=mc80980714596e97a1dd28469dd72f589 Meeting number:2534 876 5158 Join from a video system or application Dial [email protected] You can also dial 173.243.2.68 and enter your meeting number. To dial from an IEEE Video Conference System: *1 2534 876 5158 Tap to join from a mobile device (attendees only) +1-415-655-0002,,25348765158## United States Toll 1-855-282-6330,,25348765158## United States Toll Free Event Day Logistics 'When guests arrive, please park in the back of the building and enter through the back door. Once inside the building, proceed to the Front Desk. From the Front Desk, walk up the stairs or take the elevators to the 2nd Floor. Once on the 2nd Floor, please follow the signs leading to the San Francisco Room.' Submit your Questions https://form.typeform.com/to/NnBZ2CRN Agenda: 5:30 – 6:00 pm: Check-in, networking, food and drinks 6:00 - 7:30 pm: Presentations by Tom Coughlin and Avery Lu 7:30 - 8:00 pm: Q&A and Networking 440 N. Wolfe Road, Suite 71, , Sunnyvale,, California, United States, 94085, Virtual: https://events.vtools.ieee.org/m/536441
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(https://r6.ieee.org/scv-tems/) is co-hosting the 2026 CES Download Event. Join us on March 5, 2026, for a Hybrid presentation. Come for a glimpse into the latest and most innovative technologies unveiled at the recent Consumer Electronics Show in Las Vegas. This is the annual IEEE (https://site.ieee.org/scv-ces/) event providing a comprehensive summary of the latest and unique tech innovations from the January 2026 Consumer Electronics Show (CES). This annual CES Download event has proven to be very popular, as many people working in related industries do not get to attend CES in Las Vegas. Presenters: Tom Coughlin and Avery Lu For details, online attendance info, and registration: https://events.vtools.ieee.org/m/536441 Plug and Play Tech Center, 440 N Wolfe Road, Sunnyvale, California, United States, 94085, Virtual: https://events.vtools.ieee.org/m/543570 |
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PLEASE NOTE THAT THIS IS FOR CHAPTER OFFICERS OF SANTA CLARA VALLEY SECTION, SAN FRANCISCO SECTION AND OAKLAND-EAST BAY SECTION ONLY Greetings! This year's officer training is being conducted for officers of San Francisco Bay Area Council at the Plug and Play Tech Center in San Jose, CA. This is meant to provide the Chapter officers with training related to the different aspects of the chapter operations. Below are some of the topics that will be covered in the training: 1. vTools 2. Concur Expense 3. Nextgen banking and reporting 4. Senior member elevation program 5. How to run an effective chapter 6. Web presence More detailed agenda will be shared soon along with presenter details. Please register using the link and save the date for the officer training. Room: 2nd floor, Silicon Valley Room, Bldg: Plug and Play Tech Center, 440 N Wolfe Rd, Sunnyvale, California, United States, 94085 |
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This is a hybrid in-person and online event. Pre-registration is required for either. In 1984, the Field Programmable Gate Array (FPGA) was invented at Silicon Valley startup Xilinx by its co-founder Ross Freeman. It was not an obviously good technology as it had serious drawbacks in speed, cost, power, and capacity. However, its novel design transformed the technology industry as it rode the wave of Moore’s Law. As this transformation was not a straight road, companies that did not recognize fundamental industry changes created by the FPGA fell by the wayside. If companies did not stretch to find new uses for this technology, or did not deploy its resources in building a new ecosystem, they also failed. Xilinx’s FPGA invention led to the major industry transformation of the Fabless semiconductor model, and step-by-step Xilinx navigated this field of potential failure. These steps tell of a company growing from a hyper-lean adrenaline-driven startup to a multi-billion-dollar success story. Not every step was correct, and certainly there was some luck. However, considerable effort was required to achieve that luck, and even more effort to capitalize on it. In this talk, IEEE Fellow Steve Trimberger will discuss change: the changing value of semiconductor scaling, the changing needs of EDA, the changing barriers to entry, the changing application of the technology, and the changing role of consultants and corporate relationships over the course of many years. These changes got us to 2026 – what change is next? Please note that an IEEE Milestone for the FPGA will be dedicated on Thu, March 12. Information about attending its dedication online will be available soon. Speaker(s): Dr. Steve Trimberger, 925 Thompson Place, Sunnyvale, California, United States, 94085, Virtual: https://events.vtools.ieee.org/m/534657 |
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Ian Walker of GMW Associates will review the development of projected-field electromagnets for device testing. Speaker(s): Ian, Agenda: 6:30 – 7:00 Socializing and Networking at Quadrant 6:55 Zoom session will be online with Waiting Room 7:00 – 7:45 Lecture begins, online and in person 7:45 – 8:00 Questions and Answers 1120 Ringwood Ct., San Jose, California, United States, 95131, Virtual: https://events.vtools.ieee.org/m/535158 |
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Celebrate International Women's Day 2026 with our virtual panel "Give to Gain: Investing in Women to Strengthen Leadership and Innovation." This engaging international dialogue brings together leaders from higher education, engineering, and IEEE WIE to explore how investing in women creates stronger leadership pipelines and accelerates innovation in STEM and beyond. Virtual: https://events.vtools.ieee.org/m/543770 |
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Join us for a talk on how SmartNICs and RDMA Power AI in the Cloud, check out an Embodied AI demo and get insights into the state of the Chapter. Training modern Large Language Models (LLMs) requires tens of thousands of GPUs acting as a single "AI Supercomputer." To build this "AI Hypercomputer," we must first address the CPU bottlenecks of traditional general-purpose networking. This talk begins by analyzing why standard TCP/IP processing limits Model Training performance and introduces the concept of "Kernel Bypass" and the role of SmartNICs in offloading network processing from the host CPU. We will explore why modern AI clusters have moved toward hardware offloads (like RDMA) to achieve the high throughput and low latency required for GPU-to-GPU communication. We will also discuss the specific challenges of running lossless transport protocols over lossy Ethernet, where congestion and packet drops can cause severe performance degradation ("tail latency") in large-scale training jobs. The session concludes by analyzing the architectural design patterns required to optimize flow control and ensure reliable delivery in massive AI infrastructure environments. Demo: Comparing Reinforcement Learning with Imitation Learning for Autonomous Warehouse Pick-and-Place using a Robotic Arm This demo simulates a last-meter warehouse picking task, inspired by Amazon/Kiva-style systems but using general-purpose robotics. The experiments explicitly contrast policy-gradient reinforcement learning methods such as PPO with imitation learning inside a physically realistic embodied-AI task built with Isaac Sim. The demo has been designed to expose where each algorithm struggles or excels due to action spaces, partial observability, contact dynamics, and reward structure. These are core issues in embodied AI. This event features a leading industry expert from Google addressing this important topic, followed by a demo on Embodied AI using Isaac Sim / Lab updates on the state of our chapter from the IEEE CIS SCV Chair. 🎤 Talk 1 The Infrastructure of AI: How SmartNICs and RDMA Power the Cloud Speaker: Sujithra Periasamy, Google 🎤 Demo and Talk Comparing Model-Free RL Algorithms for Autonomous Warehouse Pick-and-Place with Mobile Manipulation Speakers: Mayank Kapadia and Dr. Vishnu S. Pendyala, Department of Applied Data Science, College of Information, Data, and Society, San Jose State University 🎤 Talk 2 State of the Chapter Speaker: Dr. Vishnu S. Pendyala, Chair, IEEE CIS Santa Clara Valley Chapter Co-sponsored by: Vishnu S. Pendyala, San Jose State University Speaker(s): Sujithra Periasamy, Dr. Vishnu S Pendyala Room: MLK Room 225, Dr. Martin Luther King, Jr. Library (SJSU), 150 E San Fernando St San Jose, California 95112, San Jose, California, United States, Virtual: https://events.vtools.ieee.org/m/537154 |
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Silicon Metasurfaces for DNA Synthesis Abstract: Ready access to long, accurate, and diverse synthetic DNA is essential for the rapid growth of synthetic biology — a field that genetically programs living cells with new functions. Modern microarray-based DNA synthesizers can generate diverse pools of oligonucleotide (single stranded DNA) sequences in parallel. However, each sequence is produced in limited quantity, and their yields decline with increasing oligo length due to cumulative synthesis errors. These limitations complicate downstream sequence segregation and gene assembly. Attempts to address these challenges by enlarging and spacing synthesis sites farther apart reduce the total number of sequences that can be generated simultaneously, thereby compromising synthesis diversity. [] In this talk, I will introduce B-MOS (Metasurface Oligonucleotide Synthesizer for Engineered Biology) — a novel platform that integrates silicon nanophotonics with solid-phase DNA synthesis to overcome these challenges. B-MOS employs dielectric metasurfaces composed of arrays of high-index and low loss silicon nanoantennas (metasurfaces) patterned on glass as optically programmable synthesis sites. The unique optical signature of each metasurface — its spectral and polarization response — is lithographically encoded into the geometry and orientation of the silicon nanoantennas. Under global illumination, only the metasurface tuned to the wavelength and polarization of the laser absorbs the optical energy and transduces it into highly localized heat to site-selectively activate the synthesis reactions. Tuning the laser enables switching between the synthesis sites without moving parts or complex optical projection systems that lead to alignment errors. As these nanostructures support sharp (high-Q) optical resonances, crosstalk between the synthesis sites is minimized. These sharp resonances allow the dense spectral packing of independently addressable synthesis within the tunable range of the laser, thereby maximizing synthesis diversity. Using temperature as a programmable biochemical control knob, I will demonstrate site-selective enzymatic incorporation of fluorescent nucleotides onto surface-bound DNA using the enzyme terminal deoxynucleotidyl transferase. I will further discuss how integrating B-MOS with microfluidics can enable post-synthesis site-selective amplification and spatial segregation of oligo strands for reliable gene assembly. Finally, I will outline how B-MOS can be extended to RNA and peptide synthesis as well as other enzyme-driven processes. By resonant nanophotonics with programmable biochemical control, B-MOS establishes a scalable physical foundation for high-precision biomolecular manufacturing and next-generation molecular technologies. Speaker: Dr. Punnag Padhy Postdoctoral Scholar Department of Materials Science and Engineering Stanford University AGENDA: Thursday March 19, 2026 11:30 AM: Networking, Pizza & Drinks Noon -- 1 pm: Seminar Please register on Eventbrite before 9:30 AM on Thursday March 19, 2026 $4 IEEE members $6 non IEEE members (discounts for unemployed and students ) Bldg: ==> Use corner entrance: Kifer Road / San Lucar Court ==> Do not enter at main entrance on Kifer Road, EAG Labs, 810 Kifer Road, Sunnyvale, California, California, United States, 95051 |
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Speaker(s): Roberto Morabito, Room: 4021, Bldg: Sobrato Campus for Discovery and Innovation, Santa Clara University, 500 El Camino Real, Santa Clara, California, United States, 95054, Virtual: https://events.vtools.ieee.org/m/539764 |
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[]Come join us for lunch, and this important talk - IN-PERSON ONLY Co-packaged optics (CPO) are heterogeneous integration packaging methods to integrate the optical engine (OE) which consists of photonic ICs (PIC) such as the photodiode laser, etc. and the electrical engine (EE) which consists of the electronic ICs (EIC) such as the laser driver, transimpedance amplifier, etc. as well as the switch ASIC (application specific IC). The advantages of CPO are: (a) to reduce the length of the electrical interface between the OE/EE (or PIC/EIC) and the ASIC, (b) to reduce the energy required to drive the signal, and (c) to cut the latency which leads to better electrical performance. In the next few years, we will see more implementations of a higher level of heterogeneous integration of switch, PIC and EIC, whether it is for performance, form factor, power consumption or cost. The content of this lecture: — Silicon Photonics — Data Centers — Optical Transceivers — Optical Engine (OE) and Electrical Engine (EE) — OBO (on-board optics) — NPO (near-board optics) — CPO (co-packaged optics) — 3D Integration of the PIC and EIC — 3D Heterogeneous Integration of PIC and EIC — 3D Heterogeneous Integration of ASIC Switch, PIC and EIC — 3D Heterogeneous Integration of ASIC Switch, PIC and EIC with Bridges — 3D Heterogeneous Integration of ASIC Switch, EIC and PIC embedded in Glass-core Substrate — Various Forms of CPO Speaker(s): John Lau, 673 So Milpitas Blvd, Milpitas, California, United States, 95035 |
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[] Designing Your Early Career: LinkedIn, Resume & Interview Strategy That Works Breaking into today’s competitive job market requires more than technical excellence. It requires clarity, positioning, and the ability to communicate your value with confidence. In this practical and engaging session, career strategist Shima Ghaheri shares how hiring managers actually evaluate candidates — and how students and early-career professionals can strategically present their academic work, projects, internships, and experiences to stand out. Participants will learn how to: - Build a LinkedIn profile that signals clarity and direction - Structure resumes around measurable impact rather than task lists - Approach interviews with preparation and strategic storytelling - Translate technical competence into compelling professional narratives Designed specifically for college students and entry-level professionals, this session offers actionable tools to move from being “qualified on paper” to being selected with confidence. By making hiring systems more transparent, the session aims to reduce opportunity gaps and empower participants to compete through preparation, clarity, and strategy. Whether you are preparing for internships, full-time roles, or your next career move, this session will equip you with frameworks you can implement immediately. Co-sponsored by: IEEE SFV Virtual: https://events.vtools.ieee.org/m/541336 |
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Monthly AdCom meeting: 1. Welcome - Hualiang 2. Symposium status update - Annette/Paul/Hualiang 3. Education outreach status - Masha/Azmat/Hualiang 4. Chapter Storage - Hualiang XXXX NOT 5. Monthly talk preparation - Chandan/Luu 6. Chapter website update - XXXX NOT Venkatesh/Claire/Paul 7. Senior member advancement - Dwayne Xxxx NOT 8: Election 2026 9: Open discussion - All Agenda: Monthly AdCom meeting: 1. Welcome - Hualiang 2. Symposium status update - Annette/Paul/Hualiang 3. Education outreach status - Masha/Azmat/Hualiang 4. Chapter Storage - Hualiang XXXX NOT 5. Monthly talk preparation - Chandan/Luu 6. Chapter website update - XXXX NOT Venkatesh/Claire/Paul 7. Senior member advancement - Dwayne Xxxx NOT 8: Election 2026 9: Open discussion - All Virtual: https://events.vtools.ieee.org/m/544928 |
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Chiplet and disaggregated architectures are rapidly becoming mainstream across applications from edge to server. Yet the resulting design complexity exceeds the capabilities of today’s tools, flows, and methodologies—particularly when aiming for highly optimized solutions at scale. Augmented Intelligence, the combination of human expertise and machine intelligence, offers a transformative approach to this challenge. By assigning strategic, high-level decision-making to engineers and delegating computationally intensive, iterative tasks to AI, this framework enables multi-level and multi-domain optimization. The result is the ability to generate a far greater number of custom-optimized designs with the same resources—delivering competitive products with higher quality and faster time-to-market. At Intel, in collaboration with partners, we have developed and deployed Augmented Intelligence solutions spanning silicon to system design and hardware to software design. These efforts have demonstrated efficiency gains exceeding 90% in critical areas. In this talk, I will share practical examples and key insights from several years of applying Augmented Intelligence to end-to-end design, highlighting how human–AI collaboration is reshaping the path to innovation. There will not be any recording. Please attend in person. Speaker(s): Olena Zhu, Agenda: 5:30-6:15pm: Light Dinner/Social 6:15: Chapter Admin and then Presentation Room: Conf SJ5-1 Lake Tahoe, Bldg: Building 5, 2655 Seely Ave, Cadence campus, san jose, California, United States, 95134 |
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Synopsis: Please feel free to check out the work and thoughts of Prof. Ethem Alpaydın, Ph.D., https://mitpress.mit.edu/author/ethem-alpaydn-10375/ on Google Scholar at https://scholar.google.com/citations?user=lXYKgiYAAAAJ&hl=tr and generally on the Internet. Then, please feel free to submit your questions to Prof. Ethem Alpaydın - via Twitter by using the hashtag #ProfAlpaydinAMA and tagging @vishnupendyala - emailing vspendyala(at)hotmail(dot)com with #ProfAlpaydinAMA in the subject Selected questions will be answered by Prof. Alpaydin during the session. The audience may be able to ask follow-up questions during the session, using the Chat feature. --------------------------------------------------------------- By registering for this event, you agree that IEEE and the organizers are not liable to you for any loss, damage, injury, or any incidental, indirect, special, consequential, or economic loss or damage (including loss of opportunity, exemplary or punitive damages). The event will be recorded and will be made available for public viewing. Co-sponsored by: Vishnu S. Pendyala, SJSU Speaker(s): Dr. Vishnu S. Pendyala, Prof. Alpaydın Virtual: https://events.vtools.ieee.org/m/537179
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Pierre-Olivier Jubert of Western Digital will review the design and characterization of media used in heat-assisted magnetic recording (HAMR). Speaker(s): Pierre-Olivier, Agenda: 6:30 – 7:00 Socializing and Networking at Quadrant 6:55 Zoom session will be online with Waiting Room 7:00 – 7:45 Lecture begins, online and in person 7:45 – 8:00 Questions and Answers Quadrant Corp., 1120 Ringwood Ct., San Jose, California, United States, 95131, Virtual: https://events.vtools.ieee.org/m/544920 |
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