The Product Safety Engineering Society Bay Area Joint Section Chapter (SCV/SF/OEB) invites you to a virtual meetup of professionals interested in product safety and compliance. We will discuss the future of the chapter and plan future events. Agenda: - Business Meeting - Plan future activity of the chapter - New Officer Elections Virtual: https://events.vtools.ieee.org/m/507461

This is a hybrid in-person and online event. Pre-registration is required for either. >> DIFFERENT LOCATION FOR IN-PERSON MEETING THIS MONTH! This presentation will discuss the pioneering microprocessor R&D efforts at Bell Labs in 1976-1982 which created a new chip architecture and physical design. New test and verification methods were needed to overcome challenges in CMOS fabrication, and many of this project’s inventions were forerunners of subsequent VLSI developments: - high-speed domino circuits to reduce complex logic gate delay times, - a twin-tub CMOS process for improved power efficiency and performance, - interconnect-centric logic design for signal delay reduction, - gate-matrix layout which increased density, - 32-bit wide internal and external transfers, and - instructions which implemented certain UNIX operating system and C programming language operations As explained by Michael Condry in an (https://spectrum.ieee.org/bellmac-32-ieee-milestone), this device was designed with the intention of carrying both voice and computation into the future, and CMOS was seen as a promising—but risky—alternative to the NMOS and PMOS designs then in use. During this talk, three of the project leaders will describe how their team overcame numerous obstacles, and how they exceeded their speed goal with a 6.4 MHz device in 2.5 micrometer CMOS technology. These efforts created the BELLMAC-32 series of microprocessors, whose applications included telephony products. Their work was recognized this year with an (https://ieeemilestones.ethw.org/Milestone-Proposal:Development_of_the_Bellmac_Microprocessor,_1980). Speaker(s): Michael Condry, Sung (Steve) Mo Kang , Victor Huang 925 Thompson Place, Sunnyvale, California, United States, 94085, Virtual: https://events.vtools.ieee.org/m/507828

Free Registration (with a Zoom account; you can get one for free if you don't already have it. This requirement is to avoid Zoom bombing. Please sign in using the email address tied to your Zoom account — not necessarily the one you used to register for the event.): https://sjsu.zoom.us/meeting/register/qGy644m7StmKMra3Xs_x2g Synopsis: Please feel free to check out the work and thoughts of Prof. Alice Smith, Ph.D., https://en.wikipedia.org/wiki/Alice_E._Smith, https://www.eng.auburn.edu/~aesmith/ on Google Scholar at https://scholar.google.com/citations?hl=en&user=3WhioLIAAAAJ&view_op=list_works&sortby=pubdate, YouTube https://www.youtube.com/results?search_query=%22alice+smith%22+auburn and generally on the Internet. Then, please feel free to submit your questions - via Twitter by using the hashtag, #ProfSmithAMA and tagging @vishnupendyala - emailing vspendyala(at)hotmail(dot)com with #ProfSmithAMA in the subject - during your registration on Zoom Selected questions will be answered by Prof. Smith during the session. Audience may be able to ask follow-up questions during the session, using the Chat feature. --------------------------------------------------------------- By registering for this event, you agree that IEEE and the organizers are not liable to you for any loss, damage, injury, or any incidental, indirect, special, consequential, or economic loss or damage (including loss of opportunity, exemplary or punitive damages). The event will be recorded and will be made available for public viewing. Co-sponsored by: Vishnu S. Pendyala, SJSU Speaker(s): Dr. Vishnu S. Pendyala, Prof. Alice Smith Virtual: https://events.vtools.ieee.org/m/498694

Rethinking Chip Design to deliver Faster, Smarter, More Compact Solutions Speaker: Dr. Jiadi Zhu CEO CDimension Jiadi Zhu is the CEO and founder of CDimension, a company rethinking chip design to deliver faster, smarter, more compact solutions for the most demanding and complex computing workloads. His vision is to redefine how chips are designed, not just for higher performance, but for fundamentally better structure and efficiency. Jiadi’s technical foundation spans over a decade of work at the frontier of 2D materials, monolithic 3D integration, and device scaling. He earned his Ph.D. in Electrical Engineering from the Massachusetts Institute of Technology and has been recognized across both academia and industry for his originality in device design, novel semiconductor materials, and integration. His research–from MIT to the lab bench of CDimension–has focused on how to break architectural bottlenecks through physics-aware, layout-driven design. Jiadi’s research has been widely cited in the field and published and presented in top-tier journals and conferences, including Nature Nanotechnology and IEEE’s International Electron Devices Meeting. Jiadi’s transition from research into startup leadership has drawn attention from leaders in semiconductors, high-performance computing, and next-generation AI hardware. Today, under Jiadi’s leadership, CDimension is overcoming the limitations of traditional chip architectures and delivering significantly better performance, efficiency, and scalability across modern computing environments. AGENDA: Thursday November 13, 2025 11:30 AM: Networking, Pizza & Drinks Noon -- 1 pm: Seminar Please register on Eventbrite before 9:30 AM on Thursday November 13, 2025 $4 IEEE members $6 non IEEE members (discounts for unemployed and students ) See examplesAdd Co-sponsored by: 636940-Santa Clara Valley Section Chapter,EMB18 Bldg: ==> Use corner entrance: Kifer Road / San Lucar Court ==> Do not enter at main entrance on Kifer Road, EAG Labs, 810 Kifer Road, Sunnyvale, California, California, United States, 95051

The rapid growth of 3D advanced packaging introduces new challenges in inspection and failure analysis, where complex structures such as microbumps, redistribution layers (RDLs), and through-silicon vias (TSVs) demand reliable non-destructive testing (NDT). Conventional approaches, including Scanning Acoustic Microscopy (SAM) and X-ray imaging, are limited by noise, resolution, and defect visibility, creating barriers for reproducible and scalable analysis. To address these challenges, our work advances an AI-powered multimodal inspection framework that couples physics-informed machine learning with structured data infrastructure. A Physics-Informed Neural Network (PINN) approach enhances SAM imaging by embedding acoustic wave physics into reconstructions, producing higher-fidelity images validated through structural similarity and physical accuracy metrics. Complementing this, multimodal data fusion across SAM, X-ray laminography, optical microscopy, and CT establishes richer defect detection and cross-validation. Central to this effort is the creation of multimodality benchmark datasets built on standardized acquisition protocols, structured metadata schemas, and annotation pipelines. These datasets provide not only a foundation for AI model training but also enable reproducibility, traceability, and interoperability across future programs. Speaker(s): Navid Asadi, Virtual: https://events.vtools.ieee.org/m/498529

This virtual meeting can accommodate up to 100 attendees. While military systems in general have to operate in tough electromagnetic environments, missile programs require special attention and considerations from an EMI/EMC perspective. From environments to requirements to best practices, this presentation will discuss key focuses of EMI/EMC engineering in relation to missile programs and systems and how best to achieve success. (https://ieeemeetings.webex.com/ieeemeetings/j.php?MTID=mbb61f437f2f2fef1c8778ed46bd30bd7) https://ieeemeetings.webex.com/ieeemeetings/j.php?MTID=mbb61f437f2f2fef1c8778ed46bd30bd7 Meeting number: 2530 212 5565 Meeting password: HBnRPPXg282 Join from a video system or application Dial [email protected] You can also dial 173.243.2.68 and enter your meeting number. To dial from an IEEE Video Conference System: *1 2530 212 5565 Tap to join from a mobile device (attendees only) (tel:%2B1-415-655-0002,,*01*25302125565%23%23*01*) United States Toll (tel:1-855-282-6330,,*01*25302125565%23%23*01*) United States Toll Free Speaker(s): Flynn Lawrence, Flynn Lawrence Virtual: https://events.vtools.ieee.org/m/508800

Millimeter-wave (mmWave) power amplifiers (PAs) are critical building blocks in next-generation radar, satellite, defense, and 6G communication systems, where output power, bandwidth, and efficiency must be achieved under stringent size, weight, and power (SWaP) constraints. Among the enabling technologies, Gallium Arsenide (GaAs) and Gallium Nitride (GaN) continue to dominate due to their complementary strengths in linearity, noise performance, and high-power density. This talk will focus on design considerations unique to mmWave GaAs and GaN PAs, with particular emphasis on stability and biasing challenges at frequencies above 20 GHz. Unlike lower microwave designs, mmWave PAs are highly susceptible to low-frequency oscillations, odd-mode instabilities, and bias-induced resonances. To mitigate these, stability networks—ranging from RC shunt loading and resistive feedback to series loading and quarter-wave stabilization—must be co-optimized with matching and biasing schemes. Special attention will be given to the integration of stability networks with bias networks, where parasitics from bias chokes, decoupling capacitors, and high-impedance bias lines can introduce additional poles/zeros in the response, affecting both gain flatness and unconditional stability. The presentation will review practical approaches to stabilizing mmWave PAs without compromising efficiency or bandwidth, including the use of lossy transmission lines, broadband bias tees, and RC filtering strategies tailored for GaAs vs. GaN processes. Case studies will illustrate how bias network design impacts stability margins and overall PA performance, and how distributed versus lumped stabilization choices evolve with frequency. The session will conclude with a discussion of packaging and integration considerations, where bondwire inductances, via transitions, and LTCC/SiP bias routing play a defining role in amplifier stability at mmWave frequencies. Speaker(s): Asmita Dani, Room: 4021, Bldg: Sobrato Campus for Discovery and Innovation, Santa Clara University, 500 El Camino Real, Santa Clara, California, United States, 95054, Virtual: https://events.vtools.ieee.org/m/505939

Hosted via Google Meet - https://meet.google.com/pqw-trcy-xpg The financial industry is entering a new phase of intelligence—one where AI systems are no longer just analytical tools but autonomous collaborators capable of interpreting goals, reasoning over complex data, and taking context-aware actions. This talk explores the emergence of agentic AI systems in finance—AI architectures designed with intent, memory, and decision agency at their core. We’ll examine how these systems differ from traditional automation by introducing the concept of goal-driven autonomy: agents that plan, execute, and self-reflect across dynamic financial environments. Drawing from real-world applications such as loan underwriting, portfolio monitoring, and compliance intelligence, the session will unpack how planners, executors, and reflectors interact within an agentic loop to make transparent, auditable decisions. The discussion will also highlight enabling technologies—large language models as reasoning engines, retrieval-augmented generation (RAG+) for contextual grounding, and knowledge graphs for structured memory—and how they converge to form adaptive decision frameworks. Finally, we’ll address the critical dimensions of safety, alignment, and regulatory oversight required to operationalize agentic AI responsibly in financial ecosystems. Participants will gain a systems-level understanding of how to engineer intent into AI, design autonomous yet trustworthy financial agents, and prepare for a future where decision-making is increasingly shared between humans and intelligent systems. --------------------------------------------------------------- By registering for this event, you agree that IEEE and the organizers are not liable to you for any loss, damage, injury, or any incidental, indirect, special, consequential, or economic loss or damage (including loss of opportunity, exemplary or punitive damages). The event will be recorded and will be made available for public viewing. Speaker(s): Dhivya Nagasubramanian Virtual: https://events.vtools.ieee.org/m/508173