IEEE Women in Engineering (WIE) Santa Clara Valley is thrilled to announce complimentary tickets to the upcoming AI Infra Summit 2025 (Expo Pass Only) through our scholarship program. What We're Offering? Complimentary tickets (Expo Pass Only) to one of the year's most impactful AI infrastructure conferences, Networking opportunities with 2,500+ industry professionals and 200+ expert speakers, Access to cutting-edge sessions on AI hardware, edge computing, data centers, and enterprise AI, Professional development in the fastest-growing sector of technology Event Details (https://enotice.mmsend.com/link.cfm?r=w88U22rr5U0C68kcv3Ff8g~~&pe=TDbpWJgHzNy92pwnGpn6DVJULynuaUwmMx2aA55v2Az19Zz5QyFgYXTRHfaa2MG4PuWpQdJmxs-QyO7lMh07yQ~~&t=sokOKAWdahFLgZcuJjJI9g~~) Date: September 9-11, 2025 Location: Santa Clara Convention Center Focus: Full-stack AI infrastructure, hardware systems, edge AI, and enterprise solutions Who Can Apply? - Students pursuing STEM degrees (undergraduate & graduate) - IEEE members (WIE members preferred) looking to advance their careers in AI infrastructure - Career professionals passionate about AI technology and infrastructure Why This Matters? The AI infrastructure market is experiencing unprecedented growth, with organizations projected to invest over $1 trillion in the next five years. This summit provides unparalleled access to industry leaders, emerging technologies, and career-defining connections. Ready to Apply? Applications are now OPEN! Complete our scholarship application form and tell us how this opportunity aligns with your career goals and passion for AI infrastructure. Apply Now: (https://enotice.mmsend.com/link.cfm?r=w88U22rr5U0C68kcv3Ff8g~~&pe=QdWvfYmw6O5PGs883UUgf-Cv5NHb2pZFt-3Z_lZ23pp8zEmDpi0ZBHP5AncOfmrWv5jWfmNcy3akQK9dlQQuUw~~&t=sokOKAWdahFLgZcuJjJI9g~~) Application Deadline: July 10th, 2025 Scholarship Recipients Announced: July 20th, 2025 Contact IEEE WIE SCV team at [email protected] Co-sponsored by: YP60369 Santa Clara, California, United States

As Moore’s Law is slowing down and eventually approaching an end for conventional CMOS, new platforms for producing circuit-level innovation are desired. At the same time, it is not desirable to throw away the existing Si-CMOS infrastructure to start new. This talk presents an overview of the 10-year research program, which is a “vertical” innovative platform by “inserting” III-V layers into a conventional Si-CMOS foundry process. The talk also presents a unified compact model for generic GaN/InGaAs-based HEMTs in the context of the hybrid III-V + CMOS technology developed for future heterogeneous integrated circuits. The developed model has been implemented in a hybrid III-V/CMOS foundry PDK for designing heterogeneous circuits in III-V/Si monolithically co-integrated technology. When: Friday, June 27th, 2025 – 11:30AM to 1PM (PDT) 11:30AM - 12PM: Networking / Pizza 12PM-12:45PM: Lecture 12:45PM-12:55PM: Q&A 1PM Adjourn Bio: Dr. Xing Zhou obtained his B.E. degree in electrical engineering from Tsinghua University in 1983, M.S. and Ph.D. degrees in electrical engineering from the University of Rochester in 1987 and 1990, respectively. He has been with the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore from 1992 to 2024. His past research interests include Monte Carlo simulation of photocarrier transport and ultrafast phenomena as well as mixed-mode circuit simulation and CAD tool development. His research at NTU mainly focuses on nanoscale CMOS compact model development. His research group has been developing a unified core model for nanoscale bulk, SOI, double-gate, nanowire CMOS, as well as III-V HEMTs. He has given more than 150 IEEE EDS distinguished lectures and invited talks at various universities as well as industry and research institutions. Dr. Zhou was the founding chair for the Workshop on Compact Modeling (WCM) in association with the NSTI Nanotechnology Conference (2002–2018). He was an editor for the IEEE Electron Device Letters (2007–2016), a guest Editor-in-Chief for the special issue of the IEEE Transactions on Electron Devices (Feb. 2014) on compact modeling of emerging devices, and a member of the Modeling & Simulation subcommittee for IEDM (2016, 2017). He was an Elected Member-at-Large of EDS Board of Governors (2004–2009; 2011–2016) and served as Vice-President for Regions/Chapters (2013–2015). He has been an EDS Distinguished Lecturer since 2000. He is a Life Senior Member of the IEEE and currently serves as chair for the RS/EPS/EDS Singapore Joint Chapter. Sunnyvale, California, United States, Virtual: https://events.vtools.ieee.org/m/487617

A talk by Prof. Min-Fu Hsieh of National Cheng Kung University (NCKU), Tainan Taiwan, exploring the integration of AI in diagnosing motor faults and advancing motor design, highlighting how AI can significantly enhance the reliability and performance of electric motors in green transportation. It will delve into the use of machine learning and deep learning models to predict and prevent motor failures (e.g., inter-turn short-circuits, demagnetization, and bearing faults), which is essential for ensuring safety and reliability in transportation and industry. Furthermore, the talk will highlight AI-driven innovations in motor design, such as noise-reduction, offering insights into how AI can revolutionize traditional motor systems and contribute to ongoing improvements in predictive maintenance and design practices. Agenda: 6:30 - 7:00 Socializing and Networking at Quadrant 6:55 Zoom session will be online with Waiting Room 7:00 - 7:45 Lecture begins, online and in person 7:45 - 8:00 Questions and Answers 1120 Ringwood Ct, San Jose, California, United States, 95131, Virtual: https://events.vtools.ieee.org/m/481023