Register NOW as REGISTRATION WILL CLOSE APRIL 10th!!! IEEE SF & OEB PES will tour Ride Zum for PES Day for a unique opportunity to witness the groundbreaking integration of electric school buses with grid support technology. We will observe firsthand how their innovative fleet functions as a dual-purpose system—providing reliable student transportation while simultaneously serving as a distributed battery network that strengthens grid resilience during peak demand periods. The Vehicle-to-Grid (V2G) technology implemented by Ride Zum represents an engineering milestone, allowing buses to charge during low-tariff hours and discharge stored energy back to the grid when most needed, all without compromising school operations. This visit allows us to explore critical aspects including infrastructure readiness challenges, multi-stakeholder coordination between school districts and utility companies, and the practical hurdles overcome by early adopters in this space. The environmental benefits are substantial: reduced emissions improving community air quality, decreased fossil fuel dependence, and enhanced grid stability that accommodates more renewable energy sources. By showcasing this pioneering approach to transportation electrification, we gain valuable insights into practical applications that support both Earth Day's environmental protection goals and IEEE PES Day 2025's focus on innovative power engineering solutions for a sustainable future. AGENDA: 11:30am-1pm Lunch (TBD at a nearby location) 1:30-3:30pm Ride Zum Tour (more detailed agenda will be sent to registered and cleared attendees) Registration is due by April 10th. Ride Zum reserves the right of final approval of the list of registered attendees, their titles and organizations they represent (outside of IEEE) as part of the clearance check required for this facility. Emails will be sent to all registered attendees to confirm approval and with more detailed agenda and location. Speaker(s): Dr. Pallav Prakash, Oakland, California, United States

The Road to Gate-All-Around CMOS IEEE SSCS Distinguished Lecturer Dr. Alvin Loke [] Abstract: Despite the much debated end of Moore's Law, CMOS scaling still maintains economic relevance with 3nm finFET SoCs already in the marketplace for over a year and 2nm gate-all-around SoCs well into risk production. Modest feature size reduction and design/technology innovations co-optimized for primarily logic scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. In this tutorial, we will start with a walk through memory lane, recounting a brief history of transistor evolution to motivate the migration from the planar MOSFET to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the finFET CMOS nodes, highlighting the resulting device technology characteristics and challenges. This will set the context for motivating the introduction of the gate-all-around device architecture, namely nanoribbons or nanosheets, and unveiling the magic of how these devices are fabricated. Speaker biography: Alvin Loke is a Senior Principal Engineer at Intel, San Diego, working on analog design/technology co-optimization for Intel’s Angstrom-era CMOS. He has previously worked on CMOS nodes spanning 250nm to 2nm at Agilent, AMD, Qualcomm, TSMC, and NXP. He received a BASc from the University of British Columbia, and MS and PhD from Stanford. After several years in CMOS process integration, Alvin has since worked on analog/mixed-signal design focusing on a variety of wireline links, design/model/technology interface, and analog design methodologies. Alvin has been an active IEEE Solid-State Circuits Society (SSCS) volunteer since 2003, having served as Distinguished Lecturer, AdCom Member, CICC Committee Member, Webinar Chair, Denver and San Diego Chapter Chair, as well as JSSC, SSCL, and Solid-State Circuits Magazine Guest Editor. He currently serves as the VLSI Symposium Secretary and SSCS Global Chapters Chair. Alvin has authored invited publications including the CICC 2018 Best Paper and short courses at ISSCC, VLSI Symposium, CICC, and BCICTS. Please register to allow for proper planning. Parking structure located at 2585 Augustine Dr. 3-hour free parking Speaker(s): Dr. Alvin Loke, Agenda: 5:30pm: Networking 6:00pm: Talk 7:00pm: Event ends 2510 Augustine Dr, Santa Clara, CA 95054, Santa Clara, California, United States, 95054