Future Vision for Heterogeneous Integration from Global Perspectives, 3 days, keynote talks, working groups ... 1: Registration is $140 ($115 for IEEE members). PayPal is the credit card payments processor; please do not use your Paypal account during the payment process here. This fee is only to cover the food and beverage service costs at the event. 2: Confirmation of your registration is immediately sent. please check spam for email from: [email protected] 3: STUDENTS: Current or recent graduate students please contact academic liaison Luu Nguyen [email protected] or Hualiang Shi [email protected] with research interest and using institution domain email for registration information. 4: When you get to the Visitor Parking area, staff will guide you to available section, and to the South Tower to check in and get your badge. Speaker(s): , , , Agenda: PLEASE navigate to (https://eps.ieee.org/technology/heterogeneous-integration-roadmap/annual-hir-conference.html) FOR DETAILS/ LATEST UPDATES and speaker bios. https://eps.ieee.org/technology/heterogeneous-integration-roadmap/annual-hir-conference.html Day 1 - Wednesday February 19, 2025 Forum on AI & Energy Efficiency and Advanced Packaging Metrology 10:30 am – 10:40 am break 10:40 am – 12:10 pm 12:10 pm – 1:10 pm Lunch 1:10 pm – 1:30 pm Welcome & Agenda Review 4:35 Thursday program preview Day 2 - Thursday February 20, 2025 9:00 am – 9:05 am Welcome 9:05 am – 9:30 am HIR Vision 10:40 am – 10:50 am Break 12:00 pm – 1:00 pm Lunch 1:00 pm – 1:10 pm Contribution Recognition – Plaque Presentation 1:10 pm – 3:00 pm TWG Collaboration Meeting Team 1 3:00 pm – 3:05 pm Break 3:05 pm – 5:00 pm TWG Collaboration Meeting Team 2 5:00 pm – 6:00 pm Networking/ Wine Tasting Day 3 - Friday February 21, 2025 9:00 am – 9:10 am Welcome and Agenda Review, EPS SCV Chapter 9:10 am - 9:45 am 9:45 am – 10:20 am 10:20 am – 10:30 am Coffee Break 10:30 am – 11:05 am 11:05 am – 11:40 am 11:40 am – 12:40 am Lunch 12:40 pm – 2:30 pm TWG Collaboration Meeting Team 3 2:30 pm – 2:40 pm Break 2:40 pm – 4:30 pm TWG Collaboration Meeting Team4 4:30 pm – 4:45 pm Conference Wrap up PLATINUM SPONSOR [] SILVER SPONSOR [] BRONZE SPONSOR [] Samsung, 3655 N First Street, San Jose, California, United States, 95134

Title: Trend and Opportunities for High-Speed (GS/s) ADCs Abstract: Analog to digital converter (ADC) is a critical building block for most electronic systems. Many wideband electronic systems (such as wireless and wireline communications) favor digitization of analog signal with increasing bandwidth (>GHz) and fidelity; at the same time, demand a low area/power consumption. It leads to a great interest in high-speed ADCs in recent years. In this talk, I will describe the recent trend of high-speed (>GS/s) ADC. Many existing works leverage massively interleaved SAR ADCs. On the other hand, there are emerging opportunities to quantize the analog signal in time domain with high speed. I will introduce a few ADC architectures and/or techniques that demonstrate promises in achieving high conversion rate but at a low area and/or power consumption, including some silicon examples developed in my research group. Speaker(s): Mike Chen, Agenda: Networking: 4:00 pm - 5:00 pm (PT) Presentation: 5:00 pm - 6:00 pm (PT) Room: 116, Bldg: Bergin Hall, 500 El Camino Real, Santa Clara University, Santa Clara, California, United States, 95053