PG&E’s San Ramon Technology Center is home to Applied Technology Services (ATS), a department of about 129 engineers, specialists, technicians, and support staff dedicated to Innovation through operational technology advancement and technical problem solving. The team supports all functional areas within PG&E with core capabilities of asset condition assessment, engineering causal evaluation, inspection and equipment innovation, grid & electrification innovation, and engineering consulting. During this tour you’ll get to learn more about the ongoing work in these areas with focus on EPSS testing, Vehicle-to-Grid testing, microgrid and remote grid evaluation, and other electric distribution product testing. Wear comfortable walking shoes as you’ll also get to visit four of the SRTC electrical laboratory facilities including the high voltage dome/high current yard, modular generation test facility EV test infrastructure, microgrid and remote grid test beds, and the distribution test yard. (See agenda below.) Speaker(s): Jason Pretzlaf Agenda: 9:00-9:05 SRTC Lobby/training room sign-in 9:05-9:15 Introductions & Safety 9:15-9:45 ATS oveview/testing capabilities 9:45-10:15 Wildfire Mitigation Technology Testing - High Voltage Dome/High Current Yard 10:15-10:45 Electric Vehicles - Modular Generation Test Facility (Inside) 10:45-11:15 Microgrids and Remote Grids - Modular Generation Test Facility (Outside) 11:15-11:45 Distribution Equipment and ADMS Testing - Distribution Test Yard 11:45-12:00 Closeout Discussion San Ramon, California, United States

In recent years, the field of advanced packaging has taken center stage as the semiconductor industry pursues ever more energy efficient, high-performance, and low-cost electronic systems. While the field of advanced packaging is undergoing revolutionary technology advances today, there is little doubt that advanced packaging in the new era of Moore’s Law will offer extreme levels of die integration/bonding and begin to blur the boundary between on- and off-chip connectivity (especially in 3D architectures) due to ever denser physical I/O interfaces/bonds. This talk will address a few technical areas. First, we present a survey of recent advanced packaging technologies. Next, we discuss the emergence of panel-based glass-core packages and their potential impact on AI workloads. Further, we present a deep dive into GT’s glass-core packaging technologies, including large-area glass packages and glass-based stitch-chip technologies for digital and mm-wave electronics. Next, 3D technologies enabled by SiO2-based chiplet wafer-level reconstitution technologies for dense 3DHI technologies and selective-ALD cobalt chiplet bonding are also discussed. Speaker(s): Muhannad Bakir, Virtual: https://events.vtools.ieee.org/m/400217